Conventional photonic analog to digital converters (pADC) use a track-and-hold circuit to convert photodiode pulses to voltage signals for digitization. However, the signal to noise ratios (SNR) of current-mode integrate-and-dump pADC circuits may be limited. For example, current-mode circuits may include front-positioned 1:N dividers which inject noise and reduce SNR. In addition, current or voltage ringing within a pADC circuit may introduce memory effects and, ultimately, intersymbol interference (ISI), which may degrade overall performance and reduce bandwidth. Further, a significant amount of power for high-SNR applications may be consumed by track and hold amplifiers.